Modern integrated circuit (IC) devices are often required to provide high speed performance, whilst also providing low power consumption. To meet this two conflicting requirements, power management techniques are typically implemented to enable an IC device to be configured to operate in a plurality of modes depending on the current system requirements. For example, an IC device may be configurable to operate in a high speed (high power consumption) mode when high performance is required/desired, and to operate in a low power consumption (low speed) mode when reduced power consumption is required/desired, and/or when high performance is not required.
A challenge faced when designing digital synchronous systems is to maximise the operating speeds of the digital components whilst ensuring setup and timing violations are avoided. This challenge is particularly difficult when implementing a power management technique, since the operating conditions (e.g. voltage, etc.) that affect the ability of a digital system to operate at a certain speed are not constant. Accordingly, it is known to implement setup violation tolerant designs that are able to tolerate minor setup and timing violations.
Razor latches are one example of such a setup violation design, with the setup violation tolerant design of these latches enabling them to remain one of the most aggressive power management techniques currently in use. FIG. 1 illustrates a simplified block diagram of an example of a typical Razor latch design 100. FIG. 2 illustrates a gate level circuit diagram of the Razor latch 100 of FIG. 1. Typically, such Razor latches 100 may be provided within critical paths of an IC device, and often a plurality of such latches may be provided sequentially within a critical path. Each Razor latch 100 comprises a main flip-flop 110 arranged to receive input data 115 during normal operation of the Razor latch 100, and to sample and latch the input data 115 upon an active edge (e.g. rising edge) of a clock signal 120. The Razor latch 100 further comprises a shadow latch 125 also arranged to receive the input data 115 during normal operation of the Razor latch 100. However, the shadow latch 125 is arranged to sample and latch the input data 115 upon an active edge of a clock signal that is delayed with respect to that of the main flip-flop 110. In the illustrated example, this is achieved by way of the shadow latch 125 sampling and latching the input data 115 on the opposing edge of the clock signal 120 to that of the main flip-flop 110 (e.g. the falling edge). The outputs of the main flip-flop 110 and the shadow latch 125 are provided to a comparator 130, which is arranged to output an error signal upon a mismatch being detected between the outputs of the main flip-flop 110 and the shadow latch 125.
In this manner, if data arrives late on the input signal 115, the late data will not be sampled in time by the main flip-flop 110. As such, the main flip-flop 110 will output the ‘old’ data, resulting in a setup timing violation. However, because the shadow latch 125 is arranged to sample and latch the input signal data on a delayed clock edge, assuming the late data is received prior to this late clock edge, the shadow latch 125 will sample and latch the late, ‘new’ data. As such, the output of the shadow latch 125 will differ from the output of the main flip-flop 110 (assuming the late data comprises a change of state), which will cause the comparator 130 to output an error signal indicating the detection of late data at the input signal 115.
In the illustrated example, the Razor latch 100 further comprises a local meta detector arranged to detect meta-stability in the output of the main flip-flop 110, for example as a result of a rising clock edge and a data signal arriving at the input thereof substantially simultaneously, and to output an error signal upon detection of such meta-stability. The outputs of the local meta detector 135 and the comparator 130 are provided to an OR gate 140, which outputs an error signal indicating an error within the Razor latch 100 caused by either the late receipt of input data or by meta-stability at the output of the main flip-flop 110.
The error signals generated by each Razor latch 100 within a signal path may then be provided to a further OR gate 145, which may then output a restore signal 150 arranged to indicate whenever one of the Razor latches 100 within the signal path detects an error. This restore signal 150 may then be fed back to a multiplexor 160 within each Razor latch 100 in the signal path to cause the output value of the respective shadow latch 125 to replace the input signal 115. In this manner, the Razor latch 100 is held in its current correct state (i.e. even if late data is received, this ‘correct’ data is used). In this manner, the signal path is allowed to stabilize following a setup timing violation.
The restore signal 150 may further be used to indicate to a clock driver that a setup timing violation has been detected. For example, and as illustrated in FIG. 3, upon detection of a setup timing violation at a first Razor latch 310, the error signal output by the Razor latch 310 is propagated through an error detect tree to the clock driver 320. Upon receipt of the error signal, the clock driver 320 may then delay the next clock edge to allow the signal path to stabilise following the detection of a setup timing violation, and to prevent corrupted data from propagating to the next latch 330 along the signal path. The clock driver 320 may also be arranged to reconfigure the clock frequency to a lower clock frequency in order to prevent such setup timing violations occurring again. Alternatively, if such setup timing violations occur only occasionally at the current clock frequency, it may be deemed acceptable for the occasional setup timing violation to occur (and be recovered from as described above) in order to achieve a higher system operating frequency.
A problem with the use of such Razor latches in this manner to recover from setup timing violations is that the clock edge immediately following a setup timing violation must be postponed in order to enable late data to stabilize, and the short window of opportunity for postponing the next clock edge. In particular, where the system comprises a large error detection tree 350 and a large clock tree 360, the window of opportunity for delaying the next clock edge is made even shorter due to the time required for the signals to propagate through these trees. For example, the use of a Razor latch at a downstream end of a signal path may be made unfeasible due to there being insufficient time between the detection of a setup timing violation at that latch, and the ability to delay the next clock edge for latches located towards the upstream end of the signal path.